VHDL, verilog, design, verification, scripts, ...Adjustments to the code in order to have it compiled using the free VHDL simulator GHDL. code 
The code last was updated, on Sun Oct 25 21:45:38 JST 2009, to fix CRC (bit reversal) and some registered signals initialization during reset. Also a static RAM model was written and added.
The code last was updated, on Wed Oct 28 09:11:56 EDT 2009, to fix a bug in GHDL simulator. I had a process in the SRAM that has a few branches. One of them included positive edge detection and the others did not. This caused GHDL not to drive some signals.
The code last was updated, on Wed Oct 28 21:55:43 EDT 2009, to fix a read RAM transaction. Apparently the data going out of the RAM, during read, was not driven to the bus.
The code last was updated, on Thu Oct 29 02:23:03 EDT 2009, I fixed my ICMP packet to include a right ICMP code of 08 and re-calculated the CRC.
The code last was updated, on Sat Oct 31 05:24:09 EDT 2009, ARP packet sent as a consequence for higher layer request.
The code last was updated, on Fri Nov 6 21:10:50 JST 2009, ARP reply is sent and accepted by the VHDL IP core.
The code last was updated, on Sat Nov 7 18:46:44 EST 2009, ARP reply is sent and accepted by the VHDL IP core. ICMP reply by the core follows.
The code last was updated, on Fri Nov 13 22:04:04 EST 2009, Replacing the asynchronous SRAM with a synchronous write memory.
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