ASIC/FPGA Design and Verification Out Source Services

Simili vhdl simulator test bench with uniform random.

1. As part of an evaluation to Simili simulator, I tried to create a test-bench with uniform random generation.
   


2. The test bench uses IEEE math real library (math_real).


3. The test bench is simple. It implements a counter which is increment value is random and constraint as well. The value is in the range of 0 to 3. The value is an integer and is converted to a 4 bit vector:
   --counter plus opertor
   use IEEE.STD_LOGIC_UNSIGNED."+";
   ...
   elsif clk'event and clk = '1' then
   --int_rand := INTEGER(TRUNC(rand*16.0));
     int_rand := INTEGER(TRUNC(rand*4.0));
     cnt <= cnt + std_logic_vector(to_unsigned(int_rand, 4));
   ...
   


4. The code can be taken from code