Test control from a VHDL test bench.

1. For an AHB project, I needed a bench that would easily allow to generate stimuli to DUT and stop the test. To do that I have used two VHDL processes.


2. The very first one is a counter. It allows me to start and stop stimuli based on a clock main cycle counter.
   --process that controls the stimuli of this bench
   p_sim_count : process(hclk)
   begin
     if hclk'event and hclk = '1' then
       sim_count <= sim_count + 1;
     end if;
   end process;
   


3. Next is the stimuli process. This process also stops the simulation. The quickest way to stop the simulation, is to use assert statement. This has a side affect in terms of printing an error message into the simulation log file. ...
   wait until sim_count = 90;
   
   --stop the test
   assert false report "Test Ended from TB" severity error;
   
   end process;
   In the simulation (run with GHDL) you get a message like this:
   tb.vhd:483:8:@1432ns:(assertion error): Test Ended from TB
   ./tb:error: assertion failed
   This appears at the end of simulation, accompanied with an additional message: saying that bench has originated it, and therefor can be safely ignored.


4. To facilitate the main loop of the stimuli and control VHDL process, I use procedures. The procedures are used to instruct each of the masters to issue an AHB transaction.
   
   procedure dmai_rd(
     ch : in integer;
     ad : in std_logic_vector(31 downto 0);
     br : in std_logic;
     sz : in std_logic_vector( 1 downto 0)
   ) is
   begin
     if(ch = 0) then
       dmai0.address <= ad;
   ...
   
   The first statements simply wait for reset completion.
     begin
       wait until hresetn = '0';
       wait until hresetn = '1';
       dmai0.start <= '0';
       dmai1.start <= '0';
       wait until sim_count = 16;
       wait until hclk = '1';
   
       write(my_line, string'("TB: dma stim start master 0 access "));
       write(my_line, now);
       writeline(output, my_line);
   
       dmai0_wr(X"10000000", X"00000004", '0', "01");
       --
       wait until sim_count = 18;
       dmai0.start <= '0';
   



5. An AHB VHDL project, built of two AHB masters, one arbiter, one AHB to APB bridge and one simple APB slave. If you are interested in this project as a graduate project, contact me via mail and put in the subject: non free AHB project.