ASIC/FPGA Design and Verification Out Source Services
SD slave to flash timeout.
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For an SD slave with
Samsung flash (k9f1208)
project
I recently added to the RTL timeout support.
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During regression, the test-bench created an illegal scenario. It started a
SD slave read single block, while the SD slave DUT
was still busy, processing SD slave read block command, which had started some time earlier.
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Instead of ignoring this command, the DUT started to process it, and
got stuck. This is unacceptable and if the DUT simply ignores
the command, the SW driver will get a timeout and will try to figure
out what has been going wrong.
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Once the problem was understood, I have also fixed the test-bench.
The test-bench will monitor the SD slave data line (DAT0), before issuing a
new command. A flag, in the main configuration of this VHDL
environment, that allows to cancel this check before command issue, was added.
Note: When neither the test-bench nor the DUT drive the SD
slave data lines, a pull up keeps it high (VHDL 'H').
--check that DAT0 is 'H' before start
while(SD_OP_START_DAT_IDLE and DATA0 /= 'H') loop
wait_for_data0 <= '1';
wait for CLOCK_CYCLE;
wait for CLOCK_CYCLE;
end loop;
wait for 400 ns;
wait_for_data0 <= '0';--debug on wave
-- Read a block of data from the card
ReadBlock(std_logic_vector(to_unsigned(4, 16)), v_result, v_data, v_status, DATA3, DATA2, DATA1, DATA0, CMD, CLK, CMD_oe, DATA_oe, CMDo, data_count);
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For more details, please e mail me to
bknpk@hotmail.com .
Put SD flash in the e mail subject.
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