Release 7.1i Map H.38

Xilinx Mapping Report File for Design 'I8051_ALL'

Design Information:

test_map.ncd synt.ngd

Target Device : xc4vlx25

Target Package : ff668

Target Speed : -10

Mapper Version : virtex4 -- $Revision: 1.26.6.3 $

Design Summary:

Logic Utilization:

Number of Slice Flip Flops: 324 out of 21,504 1%

Number of 4 input LUTs: 2,288 out of 21,504 10%

Logic Distribution:

Number of occupied Slices: 1,380 out of 10,752 12%

Number of Slices containing only related logic: 1,380 out of 1,380 100%

Number of Slices containing unrelated logic: 0 out of 1,380 0%

*See NOTES below for an explanation of the effects of unrelated logic

Total Number 4 input LUTs: 2,423 out of 21,504 11%

Number used as logic: 2,288

Number used as a route-thru: 7

Number used for 32x1 RAMs: 64

(Two LUTs used per 32x1 RAM)

Number used as 16x1 ROMs: 64

Number of bonded IOBs: 100 out of 448 22%

Number of BUFG/BUFGCTRLs: 1 out of 32 3%

Number used as BUFGs: 1

Number used as BUFGCTRLs: 0

Number of DCM_ADVs: 1 out of 8 12%

Total equivalent gate count for design: 29,960