ASIC/FPGA Design and Verification Out Source Services

The following explains a basic verification for host CPU registers.

1. A basic register package should check read operations based on previous write transactions and default values on power up as well as checking correct write value and scenarios. It also should supply means to measure coverage.


2. Such a package would include same common building blocks like every verification environment such as: valid sequences of read and write transactions generator, bus functional model to capture the assorted transactions, checker and reference model.


3. The generator simply generates valid sequences of read and write transactions. Depending on DUT used, some fields in certain registers can not be written in random.


4. The connection to the DUT is done by a bus functional model (BFM). This unit is hooked up to the DUT interface and knows how to drive a transaction.


5. The reference model keeps a copy of the DUT registers. It is initialized with the very same values as the DUT is, at power-up. On write transaction, its registers are updated and if allowed written values and their order are checked, if required. On read, the value is compared against the copy, unless a no compare mask flag is set.


6. Last is a measure to say how good have our tests progress. We need to cover accesses of read and write to each register and as mentioned above if there are special cases that need to be followed.

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