ASIC/FPGA Design and Verification Out Source Services

VHDL IP Stack

This project implements the lower layers of a standard TCP/IP stack based on a free code from University of Queensland: IP stack
My first steps to understand the project, after reading the documents are:

1. Adjustments to the code in order to have it compiled using the free VHDL simulator GHDL. code   Done


2. SRAM model for AS7C4096, which is used on board. code for SRAM model   Done


3. Simple stimuli for the input RX. code   Done simple RX description


4. The CRC component is tested separately in a stand alone test-bench. crc


5. Checking the TX. TX description   Done


6. Testing the parallel port. Not Started


7. Replacing the asynchronous SRAM with a synchronous write memory. sync RAM   Done


8. Testing ICMP and ARP that supported in this project.   Done


9. Implement my own features - TBD. Not Started



10. Compilation and simulation scripts using GHDL scripts .   Done


11. Synthesis of the VHDL IP stack, using xilinx XST free tool XST .   Done


12. Verification using specman Verifcation on going



13. Recently I added a makefile for this project. It is done based on the example c code interface for GHDL
and IP TTL filter using VHDL. The makefile is described at makefile.


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Home	Download Area An extension to the systemc example from cadance of producer consumer. SD slave with an interface to Samsung flash (k9f1208).