ASIC/FPGA Design and Verification Out Source Services

A nice script to compile, elaborate and simulate a simple VHDL design.

1. Recently I needed a script to work on an AHB project. The script compiles the design, elaborates it and optionally run simulation.


2. The first part compiles the ahb VHDL library, if the directory ahb is not found. If the directory exists, the script skips its compilation.
   Next it erases work directory and remove a previous simulation executable, if any of them exists. The the design is compiled. If an error is detected, the script stops and notifies the user. The entire log file is save in cmp.log.
   The same is done with elaboration (the file is elab.log).
   If no arguments were supplied to the scripts, it stops after elaboration. Otherwise simulation may start if the first argument is dbg or run. The former also records waves. The log results are stored in ghdl.log.
   


#!/bin/bash

if [ -d "ahb" ] ; then
  echo "ahb library exists - no re-compile"
else
  mkdir ahb
  ghdl -a -fexplicit --ieee=synopsys --workdir=ahb --work=ahb iface.vhd amba.vhd
fi
if [ -d "work" ] ; then
  rm -fr work
fi
mkdir work
if [ -e tb ] ; then
  rm -f tb
fi

ghdl -i --std=93c --warn-no-vital-generic --workdir=work -P./ahb generic_ahb_arbiter.vhd apbslv.vhd apbmst.vhd ahbmst.vhd tb.vhd >& cmp.log

grep "\.vhd:[0-9]*:[0-9]*" cmp.log
if [ $? -eq 1 ] ; then
  echo "start elaboration"
  ghdl -m --warn-no-vital-generic --work=work -Pahb --workdir=work --ieee=synopsys -fexplicit TB >& elab.log
  #head -10 elab.log
  grep -v ":warning: " elab.log
else
  echo "compilation error found"
  cat cmp.log
fi

if [ -e tb ] ; then
  if [ "$1" = "dbg" ] ; then
    time=`date`
    echo "sim started at "$time
    if [ -e ghdl.vcd.gz ] ; then
      rm -f ghdl.vcd.gz
    fi
    ./tb --stop-time=100us --assert-level=error --vcdgz=ghdl.vcd.gz >& ghdl.log
    time=`date`
    echo "sim ended at "$time
  else
    if [ "$1" = "run" ] ; then
      time=`date`
      echo "sim no wave started at "$time
      ./tb --stop-time=100us --assert-level=error >& ghdl.log
      time=`date`
      echo "sim no wave ended at "$time
    else
      echo "to simulate add either dbg or run"
    fi
  fi
else
  echo "there were errors can not run"
fi

Home	VHDL IP Stack