ASIC/FPGA Design and Verification Out Source Services

Debugging VHDL conv_integer function.

1. This page shows a simple checker in VHDL. The purpose is to verify legal values ('0' or '1'), when driven on line. This work was done as part of an SD slave project.


2. In this example, when the write enable is changing and the address latch enable is high, the data is checked to be legal value.


3. In the beginning of the simulation, an illegal value is allowed.


4. The code for the checker is shown below:
   
   constant RSTASSERT_D : time := 100 ps;
   ...
   ...
   chk_ale : process (ALE, WENeg)
   begin
     if(ALE = '1') then
       if(IO7 /= '0' and IO7 /= '1') then
         assert now <= RSTASSERT_D report "Error Flash IO7 " severity error;
       end if;
       if(IO6 /= '0' and IO6 /= '1') then
         assert now <= RSTASSERT_D report "Error Flash IO6 " severity error;
       end if;
   ...
   

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