ASIC/FPGA Design and Verification Out Source Services
Package, and record array in VHDL using free simulator GHDL.
- The following short and simple VHDL tip shows the usage of a record array in VHDL. The small case is tested via the free VHDL simulator: GHDL.
- The test case is made of two VHDL files: a small package and the test-bench. Part of the package is shown below:
The
package my_package is
type enum_size is (ZERO,EIGHT,SIXTEEN, THIRTY_TWO);
type enum_direction is (RW, RD);
type reg is record
direction: enum_direction;
reg_data: std_logic_vector (31 downto 0);
reset_value: std_logic_vector (31 downto 0);
expected: std_logic_vector (31 downto 0);
size: enum_size;
end record;
type registers is array(255 downto 0) of reg;
- The main part of the test-bench is the operation of the record array:
process(clk)
variable prt_cnt : integer := 10;
variable addrv : integer;
variable my_line : line;
begin
if(clk'event and clk = '1') then
da <= da + x"00000001";
addr <= addr + 2;
--
r_reg.reg_data <= da;
a_reg(addr).reg_data <= da;
if(prt_cnt /= 0) then
prt_cnt := prt_cnt-1;
if(addr > 0) then addrv := addr-2; else addrv := 0; end if;
write(my_line, string'("dbg "));
hwrite(my_line, a_reg(addrv).reg_data);
write(my_line, string'(" "));
write(my_line, addrv);
write(my_line, string'(" at "));
write(my_line, now);
writeline(output, my_line);
end if;
end if;
end process;
- The GHDL commands to create the simulation executable:
#!/bin/bash
ghdl -a --ieee=synopsys --workdir=work --work=work pkg.vhd
ghdl -a --ieee=synopsys --workdir=work --work=work tb_1.vhd
ghdl -e --workdir=work --ieee=synopsys kuku_TSB
- To download, simply go to dowmload are (see below) and look for vhdl_record_array.tar.gz.
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