ASIC/FPGA Design and Verification Out Source Services

VHDL clock generation.

1. For a test-bench in a SD slave project I needed to generate a constant running clock for the flash.


2. The clock is generated using VHDL loop command.

...
  constant FL_CYCLEH : time := 3333 ps; --150MHz
  constant FL_CYCLEL : time := 3333 ps; --150MHz
  signal fl_clk : std_logic := '0';

...

begin

  fl_clk_p : process begin
  loop
    fl_clk <= '0';
    wait for FL_CYCLEL;
    fl_clk <= '1';
    wait for FL_CYCLEH;
  end loop;
  end process;