ASIC/FPGA Design and Verification Out Source Services

The verilog version for the SLAVE SD is entirely free. While the verilog version is far from being complete, a lot can be learned and benefited from using it.

1. The code is simple and it can be easily improved and maintained.
2. The code is synthesized friendly, tested on XILINX XST.
3. The code is updated from time to time. A release history, including waveform in VCD format, is available on site.


4. Recently the non free code has been improved to support a flash from Samsung, instead of the XILINX ROM components.
   A typical SD read, read block and write wave form can be seen at:
   wave and project description with Samsung flash (k9f1208).
   The synthesis description of the improved code can be found at: XST.
   The newest version is written in VHDL. The VHDL test-bench allows to run regression, randomize parts of the stimuli and automatically check results.
   Parts of the randomization and checks are done using bash scripts.

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SD Slave Free Code SD Master non Free Code

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