ASIC/FPGA Design and Verification Out Source Services

IP TTL filter digital design, implemented in VHDL.

1. This project implements an IP TTL filter in hardware. If an IPV4 packet is identified, the DUT checks its TTL field. Based on previous values of TTL in former packets, the machine decides if the packet is spoofed or not. The main page of this project.;


2. This page shows a simple test with multiple frames. Some are UDP and some are ARP. The wave shows that the ARP packets are ignored (drop count increment). For each packet, identified as IPV4, learning and the check for spoof is exercised.
   For more details on this project, please send an e-mail and put in the subject:
   IP TTL filter.