ASIC/FPGA Design and Verification Out Source Services

IP TTL filter digital design, implemented in VHDL.

1. This project implements an IP TTL filter in hardware. If an IPV4 packet is identified, the machine checks its TTL field. Based on previous values of TTL data collected and analyzed from former packets, the machine decides if the packet is spoofed or not. The requirement of such a filter is discussed in this link.


2. The design and the test-bench are written in VHDL. The first phase of the bench is based on an improved open core bench for UDP project. It also uses a VHDL list access scheme to read the stimuli data. This work, including a c++ IP packet generation, is also presented in this web site: link


3. This work is currently in progress. For more details please send an e-mail and put in the subject: IP TTL filter.


4. Some links for this project:
   block diagram ; flow chart ; main state machine ; basic waves ; simulation scripts ; test stimuli ; test stimuli using real network scenario; memory model ; random delay between packet drive to DUT ; TTL random generation scheme; simulation end procedure; run regression script; reference model using vhdl linked lists; ip mac address pair check;