ASIC/FPGA Design and Verification Out Source Services

IP TTL filter digital design, implemented in VHDL.

1. This project implements an IP TTL filter in hardware. If an IPV4 packet is identified, the DUT checks its TTL field. Based on previous values of TTL in former packets, the machine decides if the packet is spoofed or not. The main page of this project.;


2. This page describes the memory model used in this Spoofed packet block VHDL IP filter project. The memory implements a synchronous write. On the rising clock edge, if write enable is high, data is written to a location pointed by the address. Read data, out of the memory array, is sampled, so it is available one clock after an address change.


3. When packet info has to be saved to memory, the DUT tries to save it in the location of its second IP byte. This is to say that the second byte of a source IP of the incoming packet (example 192.168.0.190 168), will be used in a hash start search in the Low Significant Bits of the address. If this location is occupied, it will try to write it to the next available place after the second IP byte.
   
   


4. The larger the memory the more time after reset has to be wait. One of the memory bits is a flag. This flag indicates to the main state machine if a given memory location is free or used. So upon reset, the machine frees all the memory. This is done by writing zero to all of the memory space.
   
     ...
     begin
       if rising_edge(rx_clk) then
         init_rstm <= reset;
         init_rstp <= init_rstm;
         init_rstq <= init_rsti;
         init_weaq <= init_weai;
         qo <= do;
         if(init_rstq = '1') then --init flag
           mem_array(conv_integer(init_weaq)) <= c_mem_0;
         elsif(we = '1') then
           mem_array(conv_integer(addr)) <= di;
         end if;
       end if;
     end process;--p_clk
   
     do <=
       c_mem_0 when init_rstq = '1' else mem_array(conv_integer(addr));
     
   


5. The memory size is printed on simulation start. The process is done only once, because there is a wait statement at its end.
   
     p_dbg : process
     variable my_line : line;
     begin
       write(my_line, init_weaq'path_name);
       write(my_line, string'(" max ram "));
       write(my_line, g_ram_max);
       writeline(output, my_line);
       wait;
     end process;
   



6. For more details on this project, please send an e-mail and put in the subject:
   IP TTL filter. discussed in this link.
   
   Where and Why use such a filter.