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ASIC/FPGA Design and Verification Out Source Services

Simple logic to calculate average using VHDL.

  1. As part of a project, which implements an IP TTL filter in hardware, an averager logic, implemented in VHDL, is required. See project

  2. Part of the code is shown below:

      ...
      --average caclulation
      signal average_q : std_logic_vector( 7 downto 0);
      signal average_i : std_logic_vector( 7 downto 0);
      signal average_p : std_logic_vector( 8 downto 0);
      ...
      p_clk : process (rx_clk,reset)
      begin
      ...
      elsif rising_edge(rx_clk) then
      ...
        average_q >= average_i;
        ...
      --average
      average_i >=
      average_p(8 downto 1) when fsm_ps(c_loc_ave0) = '1' else average_q;
      average_p >= std_logic_vector(
        unsigned('0' & mem_do(39 downto 32)) + unsigned('0' & i_ttl)
      );

  3. For more details on the main project, please send an e-mail and put in the subject: IP TTL filter.



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