ASIC/FPGA Design and Verification Out Source Services
VHDL SD CRC16 function.
-
For a test-bench in a SD slave
project
I needed to calculate CRC16 in VHDL. For that I wrote a function and will describe it in this page.
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The CRC function receives data and number of bits to work on.
The CRC is calculated using a simple for loop.
For debug I only print a few results in the start and end of the calculation.
- function f_CRC16(
data : std_logic_vector; nbits : in std_logic_vector
- ) return std_logic_vector is
- variable v_crc_reg : std_logic_vector(15 downto 0);
- variable v_crc_temp : std_logic_vector(15 downto 0);
- variable v_this_bit : integer;
- variable v_tmp : integer;
- variable my_line : line;
- variable result : std_logic_vector(15 downto 0);
- variable data_d : std_logic_vector(data'length-1 downto 0) := data;
- begin
- v_crc_reg := (others => '0');
- for v_this_bit in 1 to f_dbg_conv_i(nbits) loop
- v_crc_temp := v_crc_reg;
- v_crc_reg(15 downto 1) := v_crc_temp(14 downto 0);
- v_crc_reg(0) := (data(f_dbg_conv_i(nbits)-v_this_bit) xor v_crc_temp(15));
- v_crc_reg(5) := (v_crc_temp( 4) xor v_crc_reg(0));
- v_crc_reg(12) := (v_crc_temp(11) xor v_crc_reg(0));
- --dbg pini
- if(v_this_bit <= 2 or v_this_bit >= f_dbg_conv_i(nbits)-2) then
- write(my_line, string'("CRC16 dbg reg= "));
- hwrite(my_line, v_crc_reg);
- write(my_line, string'(" N= "));
- v_tmp := f_dbg_conv_i(nbits)-v_this_bit;
- write(my_line, v_tmp);
- write(my_line, string'(" di= "));
- write(my_line, data(v_tmp downto v_tmp));
- writeline(output, my_line);
- end if;
- --dbg pini
- end loop;
-
- result := v_crc_reg;
- return result;
- end f_CRC16;
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For more details, please e mail me to
bknpk@hotmail.com .
Put SD flash in the e mail subject.
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