ASIC/FPGA Design and Verification Out Source Services

A VHDL example implementing list (is access record).

1. This examples demonstrates how to create lists in VHDL. This may be useful in implementing a FIFO quickly in a test-bench.
   I used list style coding to read an unknown number of bytes, during simulation at time 0, from a file. The data is to be later driven to a DUT. read from file into a list.


2. The list item has two fields, data to be driven to DUT and a next item pointer for list manipulation.


3. The simulation is ended using an assert error statement. The code has been tested using ghdl. The code and compilation script is shown below:
   

#!/bin/bash

if [ -d "work" ] ; then
  rm -fr work
fi
mkdir work

ghdl -i --std=93c --workdir=work tb_is_access.vhd
ghdl -m --work=work --workdir=work --ieee=synopsys tb_is_access

./tb_is_access --assert-level=error




1. LIBRARY ieee;
2. USE ieee.std_logic_1164.ALL;
3. use STD.textio.all;
4. use IEEE.std_logic_textio.all;
6. use ieee.numeric_std.all;
7. use ieee.STD_LOGIC_UNSIGNED.conv_integer;
9. ENTITY tb_is_access IS
10. END tb_is_access;
12. ARCHITECTURE beha OF tb_is_access IS
14. type fifo_item; -- the item
15. type fifo_item_ptr is access fifo_item; -- pointer to item
16. type fifo_item is record -- full definition of item
17. data : std_logic_vector(7 downto 0);
18. next_rec : fifo_item_ptr;
19. end record;
21. BEGIN
23. --Read process
24. process
25. variable j : integer;
26. variable v : std_logic_vector(7 downto 0);
28. variable new_pkt : fifo_item_ptr;
29. variable tmp_ptr : fifo_item_ptr;
30. variable fifo_ptr: fifo_item_ptr := null;
32. variable my_line : line;
33. begin
34.   v := (others => '0');
35.   for j in 0 to 8 loop
36.     if(j = 0) then
37.       new_pkt := new fifo_item;
38.       new_pkt.data := v;
39.       new_pkt.next_rec := null;
40.       fifo_ptr := new_pkt;
41.     else
42.       new_pkt := new fifo_item;
43.       new_pkt.data := v;
44.       new_pkt.next_rec := null;
45.       tmp_ptr := fifo_ptr;
46.       
47.       --write(my_line, string'("dbg "));
48.       --hwrite(my_line, new_pkt.data);
49.       --writeline(output, my_line);
50.       
51.       while(tmp_ptr.next_rec /= null) loop --find last
52.         tmp_ptr := tmp_ptr.next_rec;
53.       end loop;
54.       tmp_ptr.next_rec := new_pkt;
55.     end if;
56.     v := std_logic_vector(unsigned(v) + "00000001");
57.   end loop;
58.   wait for 10 ns;
59.   tmp_ptr := fifo_ptr;
60.   while(tmp_ptr.next_rec /= null) loop
61.     write(my_line, string'("dbg "));
62.     hwrite(my_line, tmp_ptr.data);
63.     write(my_line, string'(" time "));
64.     write(my_line, now);
65.     writeline(output, my_line);
66.     
67.     tmp_ptr := tmp_ptr.next_rec;
68.   end loop;
69.   
70.   assert false report "end of test" severity error;
71. end process;
73. end beha;