ASIC/FPGA Design and Verification Out Source Services
A VHDL example that reads data from file and stores it in a list.
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The purpose of this code is to read data from a file, parse it, store the data
in a list at simulation time 0. Later on the data is retrieved in a FIFO style.
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The read is done based on
Very simple, VHDL standalone bench, to demonstrate text file read
and
lists in VHDL.
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The requirements are to read lines of hex data bytes separated by spaces and
store it in a list. Drive the data to DUT. This is done in a single VHDL process.
The input file is of the following format:
ff ff ff 22 22 22 00 0c 29 b4 41 b0 08 00 45 00
00 23 00 00 40 00 40 11 75 68 c0 a8 00 b4 01 02
03 04 00 00 00 35 00 0f d2 3b 55 44 50 44 61 74
The generation of the network stimuli data is explained at:
multi protocol packets cpp packet generator.
and
simple TCP cpp packet generator.
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The read and drive process runs continuously. There is no wait
statement, once the file content is read to the list. Instead a boolean is
used to instruct the process to wait for clock once read file into a list
ends.
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For more information, please send me a mail and put in the subject:
read and drive vhdl list.
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.NUMERIC_STD.ALL;
- use work.axi.all;
- use work.ipv4_types.all;
- use work.arp_types.all;
- use STD.textio.all;
- use IEEE.std_logic_textio.all;
- ENTITY UDP_complete_nomac_tb IS
- END UDP_complete_nomac_tb;
- ARCHITECTURE behavior OF UDP_complete_nomac_tb IS
- type fifo_item; -- the item
- type fifo_item_ptr is access fifo_item; -- pointer to item
- type fifo_item is record -- full definition of item
- data : std_logic_vector(7 downto 0);
- indx : integer;
- next_rec : fifo_item_ptr;
- end record;
- ...
- BEGIN
- --read a packet stimuli file
- process
- file fp : text;
- variable new_pkt : fifo_item_ptr;
- variable tmp_ptr : fifo_item_ptr;
- variable fifo_ptr: fifo_item_ptr := null;
- variable fifo_first : boolean;
- variable read_first : boolean := false;
- variable fifo_add : boolean;
- variable pkt_cnt : integer;
- variable file_read : boolean := false;
- variable line_content : string(1 to 47);
- variable line_num : line;
- variable j : integer := 0;
- variable p : integer := 1;
- variable d : std_logic_vector(7 downto 0);-- data
- variable char : character:='0';
- --debug
- variable my_line : line;
- variable my_cnt : integer;
- begin
- if(file_read) then
- wait until clk_int'event and clk_int = '1';
- if(not read_first) then
- tmp_ptr := fifo_ptr;
- read_first := true;
- end if;
- if(fifo_read = '1') then
- if(tmp_ptr.next_rec /= null) then
- fifo_data <= tmp_ptr.data;
-
- --write(my_line, string'("dbg "));
- --hwrite(my_line, tmp_ptr.data);
- --write(my_line, string'(" "));
- --write(my_line, now);
- --writeline(output, my_line);
-
- tmp_ptr := tmp_ptr.next_rec;
- else
- fifo_data <= (others => 'X');
- end if;
- end if;
- else
- fifo_first := true;
- pkt_cnt := 0;
- my_cnt := 0;
- file_open(fp,"vhdl_stim.txt", READ_MODE);
- while not endfile(fp) loop
- readline (fp, line_num);
- READ (line_num, line_content);
- --debug string length
- --write(my_line, string'("dbg "));
- --write(my_line, line_content'length);
- --writeline(output, my_line);
- for j in 1 to 47 loop
- char := line_content(j);
-
- --write(my_line, string'("dbg "));
- --write(my_line, my_cnt);
- --write(my_line, string'(" "));
- --write(my_line, char);
- --writeline(output, my_line);
- --my_cnt := my_cnt + 1;
-
- fifo_add := false;
- case char is
- when '0' =>
- if(p = 1) then d := "00000000"; p := 16;
- else d := d or "00000000"; p := 1; fifo_add := true;
- end if;
- when '1' =>
- if(p = 1) then d := "00010000"; p := 16;
- else d := d or "00000001"; p := 1; fifo_add := true;
- end if;
- ...
- when 'e' | 'E' =>
- if(p = 1) then d := "11100000"; p := 16;
- else d := d or "00001110"; p := 1; fifo_add := true;
- end if;
- when 'f' | 'F' =>
- if(p = 1) then d := "11110000"; p := 16;
- else d := d or "00001111"; p := 1; fifo_add := true;
- end if;
- when others =>
- fifo_add := false;
- end case;
- if(fifo_add) then
- new_pkt := new fifo_item;
- new_pkt.indx := pkt_cnt;
- new_pkt.data := d;
- new_pkt.next_rec := null;
- if(fifo_first) then
- fifo_first := false;
- fifo_ptr := new_pkt;
- else
- tmp_ptr := fifo_ptr;
- while(tmp_ptr.next_rec /= null) loop --find last
- tmp_ptr := tmp_ptr.next_rec;
- end loop; --while(tmp_ptr.next_rec /= null)
- tmp_ptr.next_rec := new_pkt;
- end if;
- --write(my_line, string'("dbg "));
- --hwrite(my_line, new_pkt.data);
- --writeline(output, my_line);
- else
- if(char = 'p') then
- pkt_cnt := pkt_cnt + 1;
- end if;
- end if;
- end loop; --for j in 1 to 47
- end loop; --while not endfile(fp)
- file_close(fp); --after reading all the lines close the file.
- file_read := true;
- end if;
-
- --stop the process from re-read
- --wait;
- end process;
- --debug
- p_1 : process(clk_int)
- variable cnt : integer := 0;
- begin
- if clk_int'event and clk_int = '1' then
- cnt := cnt + 1;
- if(cnt = 15) then fifo_read <= '1'; end if;
- if(cnt = 16) then cnt := 1; fifo_read <= '0'; end if;
- end if;
- end process;
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