ASIC/FPGA Design and Verification Out Source Services

Test control in a VHDL UDP project.

1. The main project of this test is described at: main.
2. The proces p_2 controls the test:
   1. Checks if this process is enabled. If enabled:
   2. Inserts some delay for test start.
   3. Asserts and de-asserts system reset.
   4. Inserts some delay after reset.
   5. Drives data packets as long as the packet list is not empty.
   6. Inserts some delay before ending the test.
   7. Ends the test using assert false ... severity error statement.
3. The code is shown below:
   
   p_2 : process
   variable cnt : integer := 0;
   variable j : integer := 0;
   begin
     wait until clk_int'event and clk_int = '1';
     if(not fifo_read_en) then
       wait;
     end if;
     assert false report "start fifo drive" severity warning;
     
     for j in 1 to 31 loop
       wait until clk_int'event and clk_int = '1';
     end loop;
     reset_1 <= '1';
     for j in 1 to 9 loop
       wait until clk_int'event and clk_int = '1';
     end loop;
     reset_1 <= '0';
     for j in 1 to 4 loop
       wait until clk_int'event and clk_int = '1';
     end loop;
     
     mac_tx_tready_1 <= '0';
     mac_rx_tvalid_1 <= '0';
     mac_rx_tlast_1 <= '0';
     for j in 1 to 7 loop
       wait until clk_int'event and clk_int = '1';
     end loop;
     
     while(fifo_done = '1') loop
       --start to send packets
       fifo_read <= '1'; --fifo read
       wait until clk_int'event and clk_int = '1';
       mac_tx_tready_1 <= '1'; --DUT signal
       mac_rx_tvalid_1 <= '1'; --DUT signal
       mac_rx_tlast_1 <= '0';
       while(fifo_last = '0') loop
         mac_rx_tlast_1 <= '0';
         wait until clk_int'event and clk_int = '1';
       end loop;
       mac_rx_tlast_1 <= '1';
       wait until clk_int'event and clk_int = '1';
       mac_rx_tvalid_1 <= '0'; --DUT signal
       mac_rx_tlast_1 <= '0'; --DUT drive last
       fifo_read <= '0'; --fifo read
       --packet send ended
       for j in 1 to 7 loop --TO DO randomize
         wait until clk_int'event and clk_int = '1';
       end loop;
     end loop;--while(fifo_done = '1')
     
     --wait before end
     for j in 1 to 31 loop
       wait until clk_int'event and clk_int = '1';
     end loop;
     assert false report "simulation ended okay from process p_2" severity error;
     
   end process;
   
   
4. For more information, please send me a mail and put in the subject: read and drive vhdl list.