ASIC/FPGA Design and Verification Out Source Services

Use vhdl wait to select between precesses.

1. While working on a VHDL example, which reads data from a file and drive it to DUT, I needed to easily select between an existing drive to my new drive from file. The work was to read packet data from file and drive it to a DUT. The DUT and test bench is based on the open cores UDP project.


2. The development was done in phases. First I checked my ability to read from a file. Next I figured out how to store and retrieve the data into a list: implementing lists in vhdl
   Then I started to integrate every thing in the UDP open cores bench.


3. I did it in two separate processes. This way I could see the signals of the new process and the original ones in the early phases of the development. When my code was mature enough, I started to select between the two processes and this is what this page is all about.


4. I declared a new signal (signal and not constant, because I may want to do the changes on the fly):
   signal fifo_read_en : boolean := true;
   
   Then each process has this code on the beginning:
   p_2 : process
   variable cnt : integer := 0;
   variable j   : integer := 0;
   begin
     if(not fifo_read_en) then
       wait;
     end if
   ...
   
   




An AHB VHDL project, built of two AHB masters, one arbiter, one AHB to APB bridge and one simple APB slave. If you are interested in this project as a graduate project, contact me via mail and put in the subject: non free AHB project.