ASIC/FPGA Design and Verification Out Source Services
Some tips how to print debug message from VHDL.
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This site shows, in quite a few pages, how to print debug messages from
VHDL. As an example is the following page:
print hierarchal path.
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Recently I worked on an AHB project. I had many errors to debug in the
initial bring up. Part of them were better debugged with print messages. The project
contained some VHDL records, which GHDL (free VHDL simulator) does not dump to
VCD wave.
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The very first thing to do is to declare the libraries.
-- pragma translate_off
use std.textio.all;
use IEEE.STD_LOGIC_TEXTIO.all;
-- pragma translate_on
Next is to consider the appropriate way of print. If the print is part of an assert
then matters are simple.
assert false report "procedure dmai_rd wrong channel" severity error;
If you print from a process, a line variable has to be declared.
comb : process(ahbi, dmai, rst, r)
...
-- pragma translate_off
variable my_line : line;
-- pragma translate_on
begin
The next example prints a message header, which includes an hierarchal
path name, signal names (strings), vectors in hexadecimal, as well as regular
signals. Since I had a signal named hwrite, I needed to give a full
path name to library hwrite function. Note that hwrite works on nibbles.
In my case I needed to concatenate two bits.
I used image attribute to print a
single standard logic signal. At the end of the message, the current simulation
time is printed.
- -- pragma translate_off
- write (my_line, rst'path_name);
- write(my_line, string'(" hready="));
- write(my_line, string'(Std_ULogic'image(ahbi.hready)));
- write(my_line, string'(" htrans="));
- IEEE.STD_LOGIC_TEXTIO.hwrite(my_line, "00" & htrans);
- write(my_line, string'(" grant="));
- write(my_line, string'(Std_ULogic'image(ahbi.hgrant)));
- write(my_line, string'(" "));
- write(my_line, now);
- writeline(output, my_line);
- -- pragma translate_on
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In a function, I needed to print an integer, which is fairly simple.
...
c := 0; p := 1;
for j in 0 to (vin'length - 1) loop
if(vin(j) = '1') then c := c + p; end if;
p := p * 2;
end loop;
write(my_line, string'("dbg f_std_to_int "));
write(my_line, c);
write(my_line, string'(" "));
write(my_line, p);
write(my_line, string'(" "));
write(my_line, now);
writeline(output, my_line);
return c;
...
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The above mention AHB project, was made of two AHB masters, one arbiter,
one AHB to APB bridge and one simple APB slave. If you are
interested in this project as a graduate project, contact me via mail
and put in the subject: non free AHB project.
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