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All about printing the instance name from a VHDL component.

1. While it is simple in VERILOG (%m in the display system function), in VHDL a bit more code writing is required.
$display("dbg instance name %m at %d", $time);
An example how to print an instance name in systemc is also available on this site.



2. The importance of such debug information is when a design contains many instances of the very same component.


3. First text IO library has to be called and line variable should be declared. Please refer to print example to see details.


4. Next you have to select between two options: One is: instance name only in debug string and the other option gives more information such as entry and architecture names.


5. Syntax example is given below:


1. if(newByte = '1') then
   
2.   write (my_line, string'("path "));
   
3.   write (my_line, clk'path_name);--short
   
4.   write (my_line, string'(" "));
   
5.   writeline(output, my_line);
   
6.   write (my_line, string'("inst "));
   
7.   write (my_line, clk'instance_name);--long
   
8.   write (my_line, string'(" "));
   
9.   writeline(output, my_line);
   



6. The code was tried on the free GHDL simulator. GHDL output follows:


1. path :ip_stack_tsb:u_dut:mas:crcgenethrec:clk
   
2. inst :ip_stack_tsb(bhv):u_dut@stack(stack_arch):mas@ethernet(ethernet_arch):crcgenethrec@crcgenerator(crcgenerator_arch):clk
   

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