Email: bknpk@hotmail.com Phone: +972-54-7649119


V

 

This page shows how parameters can change the structure of a systemc design, during elaboration time.

  1. This small exercise, which I did, in order to practice and study how to create parameterized modules in systemc, is described in the following pages.

  2. I decided to do a generic serial CRC module. It receives a polynum (hex number where each bit is a coefficient) and length (polynum degree) from the command line and automatically instantiate the registers, xor gates, as specified by the user, and connects them all together to from the correct DUT.
    Should an unsupported polynum is given, the simulation issues an error message and stops, via sc_stop command.
    Default values - polynum and polynum degree - do exist and the user may not specify any polynum at all from the command line.

  3. For me it was a great practice with pointers and constructors. During the debug, I had to cope with a segmentation fault, using some of the commands of the debugger, GDB, helped a lot.

  4. The design also traces signals and creates VCD files for visual wave inspection.
    Signals are recorded at the sc_main top level as well as in the parametrized CRC module.

  5. Since the debug process was more complex, relative to other systemc projects, which I did, I have also improved its make files, compilation and run bash scripts. The make file supports SCV. The script allows compilation skip, regular run or run using the debugger, GDB. If the script detects a compilation failure, it automatically launches less -p and opens the compilation log file at the very first error.

  6. The script is described at: script description .
    The code is described at: code description .
    The entire code can be downloaded from: systemc code.

    GDB tips for inspecting smart pointers (transaction class using c++ queues) is discussed in the following link.

Contact me now at:

  ...


I would be happy to offer my services. Call ASAP !


Home

memory VHDL/VPI(verilog) and systemc simulation models

UART verification project using, specman.






Search This Site


Feedback This Site




new pages on this site