This pages shows a small verification project using, specman .

1. Based on a VHDL simple UART, I created a small verification eVC.
   The DUT was first tested, using GHDL and the VHDL code and scripts can be taken from this location - UART DUT


2. This project consists of three main parts. Unit level check for the UART TX and RX. Then the DUT RX and TX are connected and tested. The later reuses both RX and TX eVC(s).
   It is shown how to connect and configure the two separate eVC(s) in the full chip environment.


3. If you would like to be notified on any changes done on this project, please send me an email. Put UART specman in the mail subject.
   


4. Project Status:
   TX coding finished.
   TX compilation finished.
   TX unit level simulation finished.
   TX unit level coverage finished.
   The code TX can be downloaded from: UART specman code
   Detailed description: UART specman description
   
   RX coding finished.
   RX compilation finished.
   RX unit level simulation finished.
   RX unit level coverage not started.
   The code RX can be downloaded from: UART specman code
   Detailed description: UART specman description
   
   UART full chip coding finished.
   UART full chip compilation finished.
   UART full chip unit level simulation finished.
   UART full chip unit level coverage finished.
   The code RX_TO_TX can be downloaded from: UART specman code
   
   Detailed description: UART specman description
   

I would be happy to offer my services. Call ASAP !

Home	a reference model in systemc using queues, from C++ STD. The open cores 1G eth UDP / IP Stack using, ncvhdl simulator