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ASIC/FPGA Design and Verification Out Source Services
A memory model, for VHDL design, build in c code and
Glib.
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This code is written with the help of this
tutorial
as well as on some examples in this web site:
GHDL c interfaces,
A very simple example to Manage C data.
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This example is made of three files:
makefile,
vhdl test-bench and c code for memory model.
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Makefiles are discussed in this web site and this one follows the same
guide lines:
random number generation.
GHDL c interfaces.
As in the former cases the makefile supports run, with and without VCD waves
as well as GDB invokation:
make run
make run GDB=gdb
make vcd
This makefile passes different switches to the compiler and linker:
GLIBCC = -I/usr/include/glib-2.0 -I/usr/lib/i386-linux-gnu/glib-2.0/include
GLIBLL = -lglib-2.0
...
EFLAGS = -m -Wl,mem_model.o -Wl,$(GLIBLL)
...
.PHONY : tb_vec
tb_vec : work-obj93.cf
$(GG) $(EFLAGS) --workdir=work --ieee=synopsys tb_vec
...
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The c code uses Glib. Parts of the
code is listed below:
- ...
- #include <glib.h>
- ...
- //memory model
- typedef struct {
- int addr;
- int data;
- } c_mem_model;
- GSList* list = NULL;
- int mem_arr_44_wr_c(int mem_free, int addr, struct ghdl_string *s) {
- ...
- //memory model
- GSList* iterator = NULL;
- c_mem_model* t_mem = NULL;
- //memory free
- if(mem_free == 1) {
- if(g_slist_length(list) > 0) {
- g_slist_free(list);
- g_free(t_mem);
- }
- return 0;
- }
- ...
- //update memory
- //if already exists, update.
- for (iterator = list; iterator; iterator = iterator->next) {
- if( ((c_mem_model*)iterator->data)->addr == addr ) {
- flg = 1;
- ((c_mem_model*)iterator->data)->data = res;
- break;
- }
- }
- //new entry
- if(flg == 0) {
- t_mem = g_new(c_mem_model, 1);//allocate
- t_mem->addr = addr;
- t_mem->data = res;
- list = g_slist_append(list, t_mem);
- }
- ...
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For more info send mail with the subject
c code memory model using Glib.
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