ASIC/FPGA Design and Verification Out Source Services
GHDL c interfaces and extensions.
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Based on the
example,
I created a makefile and changed some of the source code to run in a
standalone mode. I have also found this
page
to be helpful.
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The example is very simple. The c code is merely driving four variables of
std_ulogic type.
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I modified the c code main function to
simply drive constant data,
and not from a real parallel port:
void lecture_boutons(char boutons[4]) {
unsigned int u= SULV_0 | (SULV_1 << 8) | (SULV_Z << 16) | (SULV_X << 24);
*(int*)boutons = u;
}
I have also created a procedure that has an in variable i.e. data is
passed from VHDL to c.
--VHDL
procedure read_v (v: in std_ulogic);
attribute foreign of read_v :
procedure is "VHPIDIRECT read_v";
//C
char glb;
void read_v(char v) {
glb=v;
}
-> code
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The makefile has a few steps. First the c code is compiled, next comes vhdl
analysis and last elaboration and execution file.
Parts of the makefile are shown below:
all : boutons_c.o test_boutons
.PHONY : all
test_boutons : work-obj93.cf
$(GG) $(EFLAGS) -Wl,boutons_c.o test_boutons
.PHONY : boutons_c.o
boutons_c.o : boutons.c
$(CC) $(CFLAGS) boutons.c -o boutons_c.o
.PHONY : work-obj93.cf
work-obj93.cf : boutons.vhdl
$(GG) $(AFLAGS) boutons.vhdl
.PHONY: cleanall
cleanall :
$(shell `find . -maxdepth 1 -name "*.o" -exec rm -f {} \;`)
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