ASIC/FPGA Design and Verification Out Source Services

How to generate this kind of stimuli file for VHDL simulation in a VERILOG readmemh like format.

1. Use your assembly tool to generate a full debug information. In my case:
   asem setup_wb_cmd.s
   So you get an output with as much as debug details as the following one:
   
   
2. Run the a perl script to extract hex data for the simulation as well as debug message.



3. All files, input assembly, assembler output and perl script can be download from download area. Look for: Assembly_HowTo.tar.gz.

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CPU 8051 code (zip format)

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