ASIC/FPGA Design and Verification Out Source Services
Simple assembly code
- This is very simple program. I just want to show the flow i.e. from assembly to readmemh targeted for verilog simulation.
- This test merely writes a byte to a given address.
.text
.align 4
main:
mov r2, #0x2
ldr r3, .AD1
strb r2, [r3, #0]
.AD1:
.word 0x78000000
- First we need to compile the program and see that there is no error. If okay we should have a file named: a.outThe command for assembly compilation is: arm-elf-as ex_1.s
- Last thing to do is get object ready for our script, mentioned before. perl script The command is: arm-elf-objdump -D a.out
- The output looks as simple as our program is:
a.out: file format elf32-littlearm
Disassembly of section .text:
00000000 :
0: e3a02002 mov r2, #2 ; 0x2
4: e59f3000 ldr r3, [pc, #0] ; c <.AD1>
8: e5c32000 strb r2, [r3]
0000000c <.AD1>:
c: 78000000 stmvcda r0, {}
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