ASIC/FPGA Design and Verification Out Source Services

CPU 8051 assembly code in verilog like readmemh style

01111000 --mov r0 0x80
10000000 --
01110110 --mov @r0 0x12
00010010 --
01111000 --mov r0 0x90
10010000 --
01110110 --mov @r0 0x34
00110100 --
11100110 --mov A @r0
01111000 --mov r0 0xa0
10100000 --
11110110 --mov @r0 A
10010000 --mov @dptr, #data
10101011 --
11001101 --
11110000 --mov @dptr A
10010000 --mov @dptr, #data
00000000 --
00000000 --
11110000 --mov @dptr A
10010100 --subb A,#data
00010010
11100000 --mov A @dptr

How to generate this kind of stimuli file for VHDL simulation in a VERILOG readmemh like format. :Assembly How To

Home	CPU 8051 code (zip format) Usage of queues in C++ and discusses some motivation to implement it in verification environments.