ASIC/FPGA Design and Verification Out Source Services
Converting a compiler object dump to verilog readmemh format for simulation.
Motivation: 
 To allow co-simulation of verilog or VHDL with ARM processor.
To be able to use free tools like arm-elf.
 To notify if address increment is not 4 (will support it in the future in the script).
script input:
a.o: file format elf32-littlearm
Disassembly of section .text:
00000000 :
0: e1a0c00d mov ip, sp
4: e92dd800 stmdb sp!, {fp, ip, lr, pc}
8: e24cb004 sub fp, ip, #4 ; 0x4
script output:
command: perl TOreadmemh.pl aDump.s
e1a0c00d // 0 mov ip, sp
e92dd800 // 4 stmdb sp!, {fp, ip, lr, pc} 4 0
e24cb004 // 8 sub fp, ip, #4 ; 0x4 8 4
e24dd00c // c sub sp, sp, #12 ; 0xc 12 8
e1a00000 // 10 nop (mov r0,r0) 16 12
...
The PERL script: 
#!/bin/perl
$addr_last="";
open(FPR, $ARGV[0]) || die("open fail $ARGV[0]\n");
while(eof(FPR) != 1) {
#looking for
#address data assembly code
# 0: e1a0c00d mov ip, sp
$line=<FPR>; chomp($line);
if($line =~ /^ *([0-9a-f]*):[\t ]*([0-9a-z]*)[\t ]*([a-z]*.*)/) {
$addr=$1; $addrp=$addr; $data=$2; $assembly_code=$3;
while(length($addrp) < 4) { $addrp=" " . $addrp; }
if($addr_last ne "") {
#check address increment
#presently no support for address jumps so we notify about it
$last=hex($addr_last);
$curr=hex($addr);
if( ($curr-$last) > 4 || $last > $curr ) {
print("force an error $addr_last --> $addr\n");
};
}
print("$data \/\/$addrp $assembly_code $curr $last\n");
$addr_last=$addr;
}
}#while
close(FPR);
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