ASIC/FPGA Design and Verification Out Source Services
VHDL IP Stack
Changes to existing code required for sending an ARP frame.
- The component responsible for sending ARP packet is ethernet sender (MASSnd : ethernetSnd).
- It had all parts of the ARP done well except for the ARP data pad (all zero padded at the end).
- The core was trying to read from an initialized part of the memory instead of just writing zeros.
- A new signal was defined to drive the ARP pad data on the TX data lines. The signal is cleared when ARP pad ends and CRC starts.
- The waveform shows its operation.
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