ASIC/FPGA Design and Verification Out Source Services

Net-List Conversion

1. The methodology for normal digital design is well known. Specification, block diagram of the data path, timing of the control, RTL coding, simulation, synthesis, post synthesis and post layout simulation and static timing analysis.


2. While this is the right way of doing things, when it comes to complex digital ASIC designs, there are small number of cases where this methodology is not required.


3. I have been asked by friend to convert a post layout verilog net-list from one vendor to another. The design runs very slow, around 10 MHz, which is very slow. The design was also small in terms of gate count. So another approach has to be considered in order to make this project profitable.


4. The customer supplies the old verilog net-list with vendor libraries and test vectors. I run a script for the conversion. The output of the script is a converted net-list with new components from the new vendor. Once converted, the vectors are run again to make sure the design functions logically well.


5. The script is currently not fully complete and its control is not read as a parameter, but rather hard coded into variable inside the code, which is something I need sometimes to improve. The first phase in running the script, out of two, is to get a list of all assorted components which are in the net-list. Each component gets one entry in the output file, regardless of how many instances are in the net-list. Than the user has to manually select a replacement for each one. Unfortunately this is also hard coded presently in the code and needs to be fixed. Now the script is run again and the conversion is done.


6. Examples of how to invoke the script:
   perl net_list_conv.pl ../cpu_8051/SYN_ver/xil.v


7. net list conversion script




8. This site also includes work in system C Go to system C and C++ projects like usage of queues in C++ and discusses some motivation to implement it in verification environments.
   
   Also avialable on this site (non free): An AHB VHDL project, built of two AHB masters, one arbiter, one AHB to APB bridge and one simple APB slave. If you are interested in this project as a graduate project, contact me via mail and put in the subject: non free AHB project.