ASIC/FPGA Design and Verification Out Source Services

VHDL IP Stack compilation and simulation scripts using GHDL

This site explains how to compile, elaborate and simulate the design using free VHDL simulator GHDL.

1. Compilation is done by the a option of GHDL:
   ghdl -a --ieee=synopsys --workdir=work --work=work TB_1/tb_1.vhd TB_1/rx_gen.vhd


2. Elaboration is done using the following command:
   ghdl -e --workdir=work --ieee=synopsys ip_stack_TSB


3. Last is simulation. I recently improved the script, as shown below:
   
   #!/bin/bash
   
   time_start=`date +%s`
   Stime=$1
   if [ "$1" = "" ] ; then
     echo -n "you did "
     tput bold;
     echo -n "not "
     tput sgr0
     echo "the simulation time"
   fi
   ./ip_stack_tsb --stop-time=${Stime}us --assert-level=error --vcdgz=ghdl.vcd.gz >& ghdl.log
   time_end=`date +%s`
   time_tot=$(($time_end - $time_start))
   echo "it took "${time_tot}" seconds for simulation of "${Stime}" us to simulate"
   
   if [ -e "ghdl.log" ] ; then
     echo "simulation log was created - ghdl.log"
   else
     echo "simulation log was "
     tput bold;
     echo "not "
     tput sgr0
     echo "created - ghdl.log"
   fi
   
   if [ -e "ghdl.vcd" ] ; then
     if [ -e "ghdl.vcd.gz" ] ; then
       rm -f ghdl.vcd.gz
     fi
     gzip ghdl.vcd
   fi
   
   
   
   Note the original script and all the code can be directly downloaded at the former page under code.

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