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ASIC/FPGA Design and Verification Out Source Services

VHDL IP Stack Makefile
This is a makefile for IP stack project.

  1. #variables
  2. CC = gcc
  3. CFLAGS = -c -g
  4. #-MD
  5. SHELL := /bin/bash
  7. GG = ghdl
  8. GG_LIB = --ieee=synopsys --workdir=work
  9. AFLAGS = -a --work=work
  10. IFLAGS = -e
  11. EFLAGS = -m -Wl,g_rand.o
  13. #to override use make run RTIME=1000
  14. RTIME = 500
  15. RUN = --stop-time=$(RTIME)us --assert-level=error
  16. VCD = --vcdgz=ghdl.vcd.gz
  18. .PHONY : run
  19. run :
  20.   ./ip_stack_tsb $(RUN) |& tee ghdl.log
  21. .PHONY : vcd
  22. vcd :
  23.   ./ip_stack_tsb $(RUN) $(VCD) |& tee ghdl.log
  26. .PHONY : all
  27. all : elab exe
  29. .PHONY : exe
  30. exe : elab
  31.   $(GG) $(IFLAGS) $(GG_LIB) ip_stack_TSB
  33. .PHONY : elab
  34. elab : TB_1/tb_1.vhd TB_1/rx_gen.vhd globalconstants.vhd stack3.vhd ethernet.vhd crcgenerator.vhd ethernetsnd.vhd arp3.vhd arpsnd.vhd internet.vhd internetsnd.vhd udp.vhd icmp.vhd my_bufg.vhd MEMORY/memory.vhd MEMORY/sync_mem.vhd
  35.   $(GG) $(AFLAGS) $(GG_LIB) TB_1/tb_1.vhd TB_1/rx_gen.vhd globalconstants.vhd stack3.vhd ethernet.vhd crcgenerator.vhd ethernetsnd.vhd arp3.vhd arpsnd.vhd internet.vhd internetsnd.vhd udp.vhd icmp.vhd my_bufg.vhd MEMORY/memory.vhd MEMORY/sync_mem.vhd
  38. .PHONY: cleanall
  39. cleanall :
  40.   $(shell `find . -maxdepth 1 -name "*.o" -exec rm -f {} \;`)
  41.   $(shell `find . -maxdepth 1 -name "*.cf" -exec rm -f {} \;`)
  42.   $(shell `find . -maxdepth 1 -name "ip_stack_tsb" -exec rm -f {} \;`)
  43.   $(shell `rm work/*`)
  45. $(warning Pini's makefile)
  46. $(info CC debug = $(CC))
  ...


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