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Back to Simili VHDL simulator.

1. Recently I needed to translate one of the free projects from this site to VHDL.
   


2. Usually I use GHDL on this site. Since for this project, I need more performance, I decided to go for commercial tools, which are not too expensive.


3. Before purchasing a license, I wanted to see that it works well on my dbian machine. So I went to VHDL Simili site and downloaded their free version of the tool.


4. As root user, I executed the installation script and the installation was quick and worked well. The documentation comes as HTML or PDF.


5. Next I copied from the example directory the TLC code.
   Compilation:
   vhdlp tlc.vhd tlc_tb.vhd
   Simulation:
   vhdle -p -do a.do tlc_tb
   The do file only generates signal list (contains one line):
   add list clk car done
   


6. In Simili site (contributions) one can find a utility, that converts list to VCD (lst2vcd.c). I use it and inspect wave with gtkwave.


7. Simili comes with scripts to compile vendor libraries. I used xilinx for a project. Since the example compiles simprim and I used unisim, I also tested simil on unisim, using my own script:
   unisim compilation


8. This site also shows an example of simili vhdl simulator test bench with uniform random. link

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