Simulation of the open cores 1G eth UDP / IP Stack using,
ncvhdl simulator

1. In search for self study projects for this site, I have downloaded from the open cores site, this UDP project.


2. I first used ghdl free simulator for the job. I wanted to see if it compiles well before I go farther with this project.
   Next I compiled with cadence tool as I intend to do a small self study specman verification project.


3. The following steps are required to compile the design:
   
   1. create a cds.lib file. In my case it is simple. A library directory path and an include to standard library:
      include $CDS_INST_DIR/tools/inca/files/cds.lib
      DEFINE work ./work_lib
      
   
   
   
   
   2. Compile the design using VHDL 93 and the right order of files, packages first:
      ncvhdl -messages -v93 ../../rtl/vhdl/axi.vhd ../../rtl/vhdl/ipv4_types.vhd UDP_complete_nomac_tb.vhd ../../rtl/vhdl/*.vhd
      
   
   
   3. Inspect the log file:
      less -p "\*[EF]" ncvhdl.log
      If you want to invoke vi from within less type: v.
   
   
   4. Next step is elaboration, using the following command:
      ncelab -NOASSERT -messages UDP_complete_nomac_tb:behavior -access +rwc -ERRORMAX 1 -NOTIMINGCHECK -TIMESCALE 1ns/1ps -snapshot pk_snp
      less -p "\*[EF]" ncelab.log
      
   
   
   5. Last step is invoking the simulator:
      specrun -log specman_sim.elog -p "config gen -default_generator=IntelliGen; load ../e/test/test_debug_1; test -seed=4" ncsim -NBASYNC -batch -input pk.tcl pk_snp
      
      Note, that the specman simulation log is in a different file than default one used for the first step.
      
   
   
   6. To go to main page and to obtain code go to the following link.
   
   

Home	SD slave with an interface to Samsung flash (k9f1208). VHDL function, which generates random numbers.