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VHDL function, which generates random numbers.

1. For an SD slave project I needed to generate random numbers.


2. In some cases, I generated random number via a bash script. The motivation to do it, with script, is discussed at script


3. I found a simple VHDL module on the web, that generates random numbers and tested it. random module


4. For this project, I created a function that works the same. The web VHDL module generates a random number every clock rising edge. The function does it when called. It gets a bus width and an initial number.


5. The function is invoked, from the VHDL test file by:
   
   ...
   --data buffer initialization
   for i in 0 to wr_arr_sz-1 loop
     wr_data_bits := wr_data_bits(wr_data_bits'length-9 downto 0) &
     wr_data_tm(4) & wr_data_tm(5) & wr_data_tm(6) & wr_data_tm(7) &
     wr_data_tm(0) & wr_data_tm(1) & wr_data_tm(2) & wr_data_tm(3) ;
     if(SD_WR_DATA_INC) then
       wr_data_tm := std_logic_vector(unsigned(wr_data_tm) + "00000001");
     else
       temp_1 := wr_data_tm;
       wr_data_tm :=
       std_logic_vector(unsigned(temp_1) + unsigned(f_my_rand(8, temp_1)));
     end if;
   ...
   


6. The function is shown below:
   
   ...
   --random number
   function f_my_rand(width : integer; temp_2 : std_logic_vector)
   return std_logic_vector is
   
7.   constant temp_c : std_logic_vector(width-2 downto 0):=
     temp_2(width-2 downto 0);
     variable rand_temp : std_logic_vector(width-1 downto 0):=
     '1' & temp_c;
     variable temp : std_logic := '0';
     variable random_num : std_logic_vector(width-1 downto 0);
     variable my_line : line;
   begin
     temp := rand_temp(width-1) xor rand_temp(width-2);
     rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
     rand_temp(0) := temp;
     random_num := rand_temp;
   
8.   --if(DEBUG = '1') then
       --write(my_line, string'("f_my_rand "));
       --hwrite(my_line, random_num);
       --writeline(output, my_line);
     --end if;
     return random_num;
   end f_my_rand;
   ...
   



9. I made most of my work with the free VHDL simulator GHDL. It has a simple, yet powerful, c interface. Random can be done using c code:
   c interface example 1.
   The c code interface, VHPI, is also discussed in this web: c interface example 1. The usage in VHDL bench is simple:
   
   --generate an integer between 3..16
   rand_packet_delayi := 3 + g_rand_int_c(sim_seed, 12);
   for j in 1 to rand_packet_delayi loop
     wait until rx_clk'event and rx_clk = '1';
   end loop;