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A simple VHDL function to or all bits of a given vector.

1. While in verilog it is simple, in VHDL, a function is required.
2. I had to, in verilog to VHDL translation project, to do an or operation on all bits of standard logic vector. In verilog it is as simple as
   |status.
3. The VHDL code is shown below:
   
   package sd_constants is
      function u32_divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED;
      function or_all_bits (a : UNSIGNED) return std_ulogic;
   ...
   package body sd_constants is
   ...
      function or_all_bits (a : UNSIGNED) return std_ulogic is
         variable i : integer:=0;
         variable r : std_ulogic;
      begin
         r := '0';
         for i in 0 to a'length-1 loop
            if(a(i) = '1') then r := '1'; end if;
         end loop;
      end or_all_bits;
   ...
   

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