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This page brings forward the importance of stop on fatal error, using VHDL assert-statement.

1. The assert statement of VHDL, can be used for simulation stop. This can be in a simple case like just a normal simulation end or a fatal error detection, by the verification test-bench.
2. If the simulation is let run after a fatal error occurs, the debug time may become longer in order to isolate the exact point of failure. While this is obvious, in some cases this rule is ignored. Typical example follows.
3. The simulation stop is done using the VHDL assert statement.



bad values other then specified are not detected.
if(pkt_src_sel = 0 or pkt_src_sel = 2) then
  mem_out := rx_mem(pkt_nlen+2-rx_nibble_ix);
else
  mem_out := rx_mem(rarpnlen+2-rx_nibble_ix);
end if;

good
if(pkt_src_sel = 0 or pkt_src_sel = 2) then
  mem_out := rx_mem(pkt_nlen+2-rx_nibble_ix);
elsif(pkt_src_sel = 1) then
  mem_out := rx_mem(rarpnlen+2-rx_nibble_ix);
else
  assert false
  report "bad pkt_src_sel value=" & string'(integer'image(pkt_src_sel))
  severity failure;
end if;


4. Note: the usage of the assert statement.
5. Note: the usage of image to print an integer.



6. Sometimes it is required to ignores errors at simulation time 0. The errors in this case are, in most of these cases, are false. One can add the following condition to filter out 0 time errors:
   assert (fifo_err = "0000" or now = 0 ps)
   report "---Error fifo_err or flash FSM---" severity error;
   


7. In case of failure, printing the values of the signals helps. To print std_logic_vector either write a simple function or do the following:
   assert (fifo_err = "0000" or now <= RSTASSERT_D or ignore_err_till_first_clk > 0
   report "Error fifo_err or flash FSM " &
   string'(std_logic'image(fifo_err(3))) &
   string'(std_logic'image(fifo_err(2))) &
   string'(std_logic'image(fifo_err(1))) &
   string'(std_logic'image(fifo_err(0))) & " " &
   string'(integer'image(ignore_err_till_first_clk))
   --report "Error fifo_err or flash FSM " & string'(integer'image(conv_integer(fifo_
   severity error;
   

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