ASIC/FPGA Design and Verification Out Source Services

A simple guide describing how to print from VHDL code.

1. First call the text library:
   use STD.textio.all;
   use IEEE.STD_LOGIC_TEXTIO.all;


2. In the process declare a line variable like this:
   variable my_line : line;
   


3. Now you can print in your code. Here is an example:
   write(my_line, string'(" HMASTER_q "));
   STD.textio.hwrite(my_line, HMASTER_q);
   write(my_line, string'(" at "));
   write(my_line, now);
   writeline(output, my_line);
   


Why do I use hwrite and not write. This is because the hwrite function prints values in hex. In the design I have a signal, which is named hwrite, therefore I needed to explicitly call the function: STD.textio.hwrite...


4. Sometimes it is helpful to print typed variables. As an example consider a state machine using the following type declaration:
   -- state declarations
   type STATETYPE is (stIdle, stLowNybbleRXClkLowTime, stLowNybbleRXClkHighTime, stHiNybbleRXClkLowTime, stHiNybbleRXClkHighTime, stInvalidFrame, CHKCRC);
   signal presState: STATETYPE;
   signal nextState: STATETYPE;
   ...
   -- synopsys translate_off
   write(my_line, string'("presState "));
   write(my_line, string'(STATETYPE'image(presState)));
   write(my_line, string'(" at "));
   write(my_line, now);
   writeline(output, my_line);
   -- synopsys translate_on
   
   


5. Your print will look like this:
   grep presState ghdl.log |head
   presState stidle at 0 ns
   presState stidle at 0 ns
   presState stidle at 0 ns
   presState stidle at 60 ns
   presState stidle at 420 ns
   presState stidle at 460 ns
   presState stlownybblerxclklowtime at 500 ns
   presState stlownybblerxclkhightime at 540 ns
   presState stlownybblerxclkhightime at 620 ns
   presState stlownybblerxclkhightime at 660 ns
   


6. An example, using GHDL (a free vhdl simulator), which shows how to print follows. The code is available at the download area. Look for a file named vhdl_print_example.tar.gz
   

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