Very simple, VHDL standalone bench, to demonstrate text file read, from a VHDL bench.

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2. This VHDL shows how to read text from a file. The file contains nibble in ASCII text (1101) in each line.
   

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use STD.textio.all;

ENTITY tb_read IS
END tb_read;

ARCHITECTURE beha OF tb_read IS

    signal bin_value : std_logic_vector(3 downto 0):="0000";

BEGIN

    --Read process
    process
      file fp : text;

      variable line_content : string(1 to 4);
      variable line_num : line;
      variable j : integer := 0;
      variable char : character:='0';
    begin
    --0001
    --0010
      file_open(fp,"stim.txt", READ_MODE);
      while not endfile(fp) loop
      readline (fp, line_num);
      READ (line_num, line_content);
        for j in 1 to 4 loop
          char := line_content(j);
          if(char = '0') then
            bin_value(4-j) <= '0';
          else
            bin_value(4-j) <= '1';
          end if;
        end loop;
        wait for 10 ns; --after reading each line wait for 10ns.
      end loop;
      file_close(fp); --after reading all the lines close the file.
    wait for 10 ns;
      assert false report "end of test" severity error;
    end process;

end beha;