ASIC/FPGA Design and Verification Out Source Services

Miscellaneous Digital HW

The following presents some small VERILOG/VHDL/SPECMAN designs:

VHDL and VERILOG memory models.............................. memory model my first experience with verilator.......................... my first. an hierarchical DUT + time handeling cpp bench verilator.... my second. fastest FIFO - verilator project............................ fast FIFO. fastest FIFO - verilator project............................ DPI data drive. verilator some problems (and fix) in driving DUT............ public_flat_rw

SD slave with Samsung flash VHDL ........................... SD project CPU 8051 translation from VHDL to verilog. ................. CPU free project USB PHY. ................................................... USB free project Improving The LEON2-XST PCI Interface. ..................... PCI free project I2C master connected and tested with LEON Processor. ....... I2C free project VHDL (DUT + TB)- simple UART, tested with GHDL ............. UART free Simple example for writing BFM and virtual sequences........ Sequences VHDL + specman verification eVC for open core UDP/IP........ UDP IP free VHDL - layers of a standard TCP/IP stack ................... IP STACK free Free verilog code for a SLAVE SD ........................... SD free project CPU 8051 translation from VHDL to verilog. ................. CPU free project USB PHY. ................................................... USB free project Improving The LEON2-XST PCI Interface. ..................... PCI free project I2C master connected and tested with LEON Processor. ....... I2C free project VHDL (DUT + TB)- simple UART, tested with GHDL ............. UART free specman eRM- simple UART, tested with ncsim ................ UART free

A simple synchronization between two clock domains.......... Specman Tip This tip suggest a way to debug coverage.................... Specman Tip Mirroring some verilog signals into a vhdl test-bench....... Specman Tip Passing Information From a Monitor to a Reference Model .... Specman Tip Controlling the message logger.............................. Specman Tip Controlling e-manager ...................................... e-manager Tip Specman how code style affects performance ................. Specman Tip Specman end of test......................................... Specman Tip Specman Reference Model .................................... Specman Tip Specman generate a specman portmap from a VHDL ............. script Specman simple scoreboard................................... example Specman Sending an Item to Reference Model.................. Specman Tip Specman E1 CRC-4 calculation................................ example drive a specman state (enumerated type) to wave............. example Using AWK like regular expression within specman............ example

My First systemC program.................................... My First systemC systemC debug with SC_TIME Tip.............................. SC_TIME Tip Simple multiplier and a test-bench in systemC .............. SCmult ETHERNET packet scv RANDOMIZATION in systemC ............... SCV_packet multi protocol packet c++ generator......................... link My first simple self study cpp programs..................... link systemc parameterized CRC module............................ example ETHERNET CRC (FCS) SystemC code............................. FCS ETHERNET CRC (FCS) SystemC code............................. FCS FFT systemC project - 8 point FFT - DIT algorithm .......... FFT free code systemC butterfly for an FFT ............................... SCbutterfly Complex Multiplier using only three multipliers ............ Multiplier A reference model in systemc using queues, from C++ STD .... SCc++Qu systemC dual port RAM model ................................ SCdpram systemC FFT first stage -data store- ....................... SC data store SCV example for an AIS detector............................. SCV AIS SCV system C test bench example............................. SCV TB AIS SCV scv_pop_constraint compile ............................. SCV compilation SYSC_tlm2_getting_started_4_MM ............................. memory management SYSC simple bus example release............................. SC simple bus

Specman/Verilog Code/Examples .............................. Examples Digital Design Basics ...................................... Doc Verilog Coding Guidelines................................... Guide VPI: My First VPI Program to access verilog reg............. my first VPI. VPI: C-Program to access a verilog memory array............. array acces VPI VPI: C-Programming to drive/collect data from I2C DUT....... VPI drive mon VHPI: C-interfaces and extensions for VHDL (GHDL)........... Examples VHPI: C-code to generate random numbers VHDL (GHDL)......... rand function VHPI: A memory model, for VHDL design (c and Glib).......... Glib memory

Displaying State Machine Data With ASCII. .................. Display Record array in VHDL using free simulator GHDL.............. record tip A simple guide describing how to print from VHDL code. ..... print tip The importance of stop on fatal error using VHDL. .......... vhdl tip Printing the instance name from a VHDL. .................... instance name How to print debug message from VHDL........................ debug print Random numbers from within the VHDL bench................... random generator A VHDL example implementing list using is access............ vhdl list A VHDL example to read data to list and drive it to DUT..... file to list Use vhdl wait to select between prcesses.................... process select Test control from a VHDL test bench......................... bench control Test control in a VHDL UDP project.......................... p_2 control Spoofed packet block VHDL IP filter......................... IP filter reference model using vhdl linked lists..................... vhdl linked list

To synchronize or not to synchronize an asynchronous reset.. Tip

Debugging an AMBA based SOC design.......................... AMBA debug Tip Simulation Control from CPU in SOC.......................... simulation Tip Compiler object dump to verilog readmemh 1.................. simulation Tip Compiler object dump to verilog readmemh 2.................. simulation Tip A basic verification for host CPU registers ................ Register_Verification

Home

scripts and utilities

Download Area