ASIC/FPGA Design and Verification Out Source Services

IP TTL filter digital design, implemented in VHDL.

1. This project implements an IP TTL filter in hardware. If an IPV4 packet is identified, it checks its TTL field. Based on previous values of TTL in former packets, the machine decides if the packet is spoofed or not. The main page of this project.;


2. This page shows the block diagram of the project:
   The design is divided to two phases. In the first one, the DUT identifies if the incoming packet is an IPV4 packet. If it is IPV4, its IP source address and TTL fields are extracted. In the second phase, the ttl is inspected per each IP.
   There are two main states namely:learning and TTL check. In learning state the incoming TTL values of incoming packets with the same source IP, are averaged.