ASIC/FPGA Design and Verification Out Source Services

IP TTL filter digital design, implemented in VHDL.

1. This project implements an IP TTL filter in hardware. If an IPV4 packet is identified, the DUT checks its TTL field. Based on previous values of TTL in former packets, the machine decides if the packet is spoofed or not. The main page of this project.;



2. Recently I added a MAC check. The idea is that every time, that I write an entry, I add its MAC address as well. So next time this entry is seen, i.e. the DUT signal indicating same IP is asserted, I check that the new indication namely, same MAC, is asserted as well.
   
   
3. In the test-bench I added a simple assertion to check and stop the simulation, if an error is detected. Note that the error indication is ignored for a short period, to avoid false alarms during reset.
   
   if(o_mac_ip_diff = '1') then
     assert now <= RSTASSERT_D
     report "ERROR detect a different mac ip pair " severity error;
   end if;