ASIC/FPGA Design and Verification Out Source Services

IP TTL filter digital design, implemented in VHDL.

1. This project implements an IP TTL filter in hardware. If an IPV4 packet is identified, the DUT checks its TTL field. Based on previous values of TTL in former packets, the machine decides if the packet is spoofed or not. The main page of this project.;



2. This page describes the regression script for this project. As described in random generation the vhdl bench randomizes some fields like, packet inter-frame delay, TTL and IP fields etc...
   While the vhdl bench randomize the assorted fields on the fly, from the vhdl simulation, it can not generate a seed, the initial value of the random sequence.
   signal rand_thrg : std_logic_vector(3 downto 0) := "0110";
   signal rand_thr : std_logic_vector(3 downto 0) := "0100";
   --random numbers generation
   signal rand_packet_delay : std_logic_vector(3 downto 0) := "0000";
   
   
3. I use a perl script to randomize those fields. The perl script use the linux $RANDOM to generate random numbers. It then converts the result to the right format, usually binary.
         $ix=index($line, "signal rand_thrg");
         if($ix >= 0) {
           $r=`./gen_rand.unx`; $r %= 16;
           $v=sprintf("%04b", $r);
           $ix=index($line, '"')+1;
           $new_l=substr($line, 0, $ix);
           print FPW ("$new_l$v\";\n");
         }
         else {
           $ix=index($line, "signal rand_thr ");
   
   


4. The next steps are to compile, simulate and check the log. If an error is detected, as discussed in simulation end, the script copy the log and the vhdl bench. Later this will be used to debug the test.
   
   For more details on this project, please send an e-mail and put in the subject:
   IP TTL filter.