ASIC/FPGA Design and Verification Out Source Services

IP TTL filter digital design, implemented in VHDL.

1. This project implements an IP TTL filter in hardware. If an IPV4 packet is identified, the DUT checks its TTL field. Based on previous values of TTL in former packets, the machine decides if the packet is spoofed or not. The main page of this project.;


2. This page discusses how test stimuli is generated. cpp packet generation, VHDL bench read and drive using lists is based on a previous work presented in this site: link


3. The VHDL bench reads a file with the following format:
   
   ff ff ff ff ff ff 00 23 18 29 26 7c 08 06 00 01
   08 00 06 04 00 01 00 0c 29 b4 41 b0 c0 a8 00 b4
   00 00 00 00 00 00 c0 a8 05 09 00 00 00 00 -- --
   p- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
   00 23 20 21 22 23 00 23 18 29 26 7c 08 00 45 00
   00 23 00 00 40 00 40 11 79 6e c0 a8 00 b4 c0 a8
   05 09 00 00 00 35 00 0f d6 41 55 44 50 44 61 74
   61 00 00 00 00 -- -- -- -- -- -- -- -- -- -- --
   p- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
   ...
   00 23 20 21 22 23 00 23 18 29 26 7c 08 00 45 00
   00 2f 00 00 40 00 40 06 79 6d c0 a8 00 b4 c0 a8
   05 09 f4 9a 26 94 00 00 00 00 00 00 00 00 50 00
   16 d0 55 86 00 00 54 43 50 44 61 74 61 00 00 00
   00 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
   p- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
   00 23 20 21 22 23 00 23 18 29 26 7c 08 00 45 00
   00 24 00 00 40 00 40 01 79 7d c0 a8 00 b4 c0 a8
   05 09 08 00 a8 a9 00 00 00 00 49 43 4d 50 44 61
   74 61 00 00 00 00 -- -- -- -- -- -- -- -- -- --
   ff -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
   l- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --