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VHDL SD slave CRC16 RTL.

1. For a test-bench in a SD slave project, I needed a CRC16 module written in VHDL. Parts of its verification is discussed at CRC16 VHDL function


2. The design is very simple. A few xor gates and some shift operations.


3. The VHDL code is shown below. For more details on this SD slave project, please e mail to bknpk@hotmail.com. Put SD flash in the subject.
   
   --
   -- Copyright (c) 1999-2000 Pinhas Krengel. Permission to use
   -- provided that this header remains intact. This software is provided
   -- with no warranties.
   --
   
   library IEEE;
   use IEEE.STD_LOGIC_1164.ALL;
   
   use ieee.numeric_std.all;
   use ieee.STD_LOGIC_UNSIGNED.conv_integer;
   
   --Calculates CRC16
   entity sd_slv_c16 is port (
       rst : in std_logic;
       clk : in std_logic;
       clr : in std_logic;
       din : in std_logic;
       cen : in std_logic;
       sft : in std_logic; --crc shift
       q : out std_logic
   );
   end sd_slv_c16;
   architecture BHV of sd_slv_c16 is
   
     signal C : std_logic_vector(15 downto 0);
     signal d : std_logic_vector(15 downto 0);
     signal dCrc : std_logic_vector(15 downto 0);
     signal i : std_logic;
   
   begin
     q <= C(15);
     i <= din xor C(15);
     d <=
     dCrc when cen = '1' else
     C(14 downto 0) & '0' when sft = '1' else
     C;
     
     dCrc <=
     (C(14 downto 12) & C(11) & C(10 downto 5) & C(4) & C(3 downto 0) & '0') xor
     ("000" & i & "000000" & i & "0000" & i);
   
   
     p_1 : process(clk, rst)
     begin
       if(rst = '1') then
         C <= (others => '0');
       elsif clk'event and clk = '1' then
         if(clr = '1') then
           C <= (others => '0');
         else
           C <= d;
         end if;
       end if;
     end process;
   
   end BHV;