Email: bknpk@hotmail.com Phone: +972-54-7649119


V

 

This page describes my first experience with verilator.

  1. In order to practice cpp (c++) verification benches, with system verilog DPI, using a verilog DUT, I decided to download verilator and do some self study exercises.

  2. First I installed the software. This is fairly simple on a debian machine:
    apt-get install verilator

  3. Next I headed to try the example, given in the manual pages of verilator. At this point my troubles, with this software, started.

    1. Setting the variable VERILATOR_ROOT. If I set it as in the manual pages, it would not compile. Based on its error messages, I selected:
      export VERILATOR_ROOT=/usr/bin

      Then I was able to compile it, with the following command and not as shown in manual pages:
      clear;/usr/bin/verilator --cc our.v --exe sim_main.cpp

    2. I switched to the object directory namely, obj_dir, and the make file would not work properly. Again the internal VERILATOR_ROOT, in the make file, was not set properly, under my debian machine. I applied the following simple patch:

      # Pini
      # VERILATOR_ROOT = /usr/bin
      VERILATOR_ROOT = /usr/share/verilator

    3. At this point all worked well. I run the simulation using the command:

      ./Vour


  4. The example, simple verilog and its cpp test-bench, as I used it for the test are listed below:

    module our;
      initial begin
        $display("Hello World ----");
        $finish;
      end
    endmodule

    The bench is as is in the example, untouched.

    #include "Vour.h"
    #include "verilated.h"
    int main(int argc, char **argv, char **env) {
      Verilated::commandArgs(argc, argv);
      Vour* top = new Vour;
      while (!Verilated::gotFinish()) { top->eval(); }
      exit(0);
    }

  ...


Home

verilator - an hierarchical verilog DUT + time handeling cpp bench

A simple c-code program to read a memory array from verilog RTL, using VPI.






Search This Site


Feedback This Site




new pages on this site