ASIC/FPGA Design and Verification Out Source Services

A simple c-code program to read a memory array from verilog RTL, using VPI.

1. This page summarizes all of my work to be able to read a verilog memory array via VPI. I'll explain the verilog and c code, compilation scripts and log messages.
   It took me a few hours to read the relevant pages in the LRM, look for examples and discussion groups in many pages on the web. So this page can save you a lot of time, if you need access to a verilog memory array from c code.


2. For the first step, I needed a simple DUT, written in verilog, which has an array. The following DUT has such an array. The elements of the array are initialized using the verilog system task $random. The content of the array is printed to simulation log file for post run check. The verilog code invokes the c code read program via the new created $s_itr task.
   
   module top;
     wire w1;
     reg [1:0] ra[0:15];
     integer ix;
   ...
     initial begin
       for(ix=0; ix <= 15; ix=ix+1) begin
         ra[ix]=$random(seed);
         $display("%d", ra[ix]);
       end
       #1
       $s_itr(ra);
   ...
   


3. Go to the next page to see a description of the c code VPI program.



4. An AHB VHDL project, built of two AHB masters, one arbiter, one AHB to APB bridge and one simple APB slave. If you are interested in this project as a graduate project, contact me via mail and put in the subject: non free AHB project.
   

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An extension to the example from cadance of producer consumer.